The Vipera framework consists of a layered architecture with components running on the host and micro-core devices. The framework manages the compilation of code, the transfer and launch of kernels on the micro-core devices, and the transfer of data. With the included vPython compiler, Vipera supports RISC-V and Xilinx MicroBlaze microcores running on the Xilinx PYNQ single-board computer (SBC), as well as the Adapteva Epiphany-III on the Adapteva Parallella SBC. The framework can also support other dynamic languages and micro-core devices through its plug-in architecture.
The following articles describe how to add support for a new micro-core device or programming language:
Adding a new device
The layered and plug-in architecture of Vipera greatly simplifies the process of adding a support for a new micro-core device. As Vipera already supports a number of different micro-core architectures, the platform specific sections of the framework have been isolated to minimise the impact of device-specific features of a target architecture.
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Adding a new programming language
Adding a new programming language to Vipera can be as easy as adding a new parser to the Olympus native code generation framework. If additional languages features over and above those provided by Olympus are required, these can be easily added to the framework. For example, new types can be added to the Abstract Syntax Tree (AST), along with their supporting code generation functions as outlined in the next article Olympus native code generation framework.
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Olympus native code generation framework
The Olympus native code generation framework consists of a compiler library, with plug-in language parsers and code generators, and a C-based abstract machine that supports dynamic code loading on micro-core devices. Olympus can support a number of different micro-cores, including RISC-V, Xilinx MicroBlaze and Adapteva Epiphany, as well as traditional CPUs such as the x86, ARM, SPARC, PowerPC and MIPS.
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